Low Power Two Stage Dynamic Comparator Circuit Design for Analog to Digital Converters

Abstract

Mixed signal systems plays major role in the communication systems. This paper presents the low power two stage dynamic latch comparator that works in greater speed with less power consumption when related to conventional two stage dynamic latch comparators. The proposed comparator consists of two stages such as dynamic latch and pre amplifier stage. S Edit, T Spice and W edit tool were used for simulating the comparator circuit in the 250nm technologies and the results show the power consumption of 5.761mW which is less compared to conventional comparator design power consumption and 5v input voltage is used for the simulation.