New clock-gating techniques for low-power flip-flops

Abstract

Two novel low power flip-flops are presented in the paper. The proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if the input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application.