An Optical Respite from the Von Neumann Bottleneck

Abstract

The high end of microprocessor performance is currently dominated by Reduced Instruction Set Computer (RISC) architectures. These machines execute one or more instructions per clock cycle. A processor such as the i8601 [1] runs with a 40MHz clock - requiring that on average an instruction must be delivered to the CPU every 25nS. With DRAM access times currently at around 100nS, timely instruction delivery has become a critical constraint on processor speed.