A high performance multi-standard Viterbi decoder

Xuying Zhao, Huang-Babg Li, Xiaoqin Wang
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引用次数: 5

Abstract

Convolutional encoder is widely applied in lots of wireless communication standards including 3G/4G mobile communications, DVB (Digital Video Broadcasting), IoT(Internet of Things) transmissions and so on. Therefore multi-standard Viterbi decoder design for the above receivers is a hot issue. In this paper, a reconfigurable high performance Viterbi decoder design is proposed for LTE, WiMAX, CDMA2000, GSM and TD-SCDMA. The proposed flexible architecture supports polynomial reconfiguration, constraint length of 5∼9, and code rate of 1/2, 1/3, 1/4. Moreover, both tail-biting and zero trellis terminating modes are supported. To reduce decoding latency and complexity, it employs the forward traceback method and sliding window pipeline technology. Simulation results show that its maximum decoding throughput is 1.15Gbps under a clock frequency of 600MHz. Finally, its area is about 0.2mm2, and the power consumption is about 46 mw, which is estimated with Synopsis DC and TSMC 28nm standard cell library.
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一个高性能的多标准维特比解码器
卷积编码器广泛应用于3G/4G移动通信、DVB(数字视频广播)、IoT(物联网)传输等多种无线通信标准中。因此,针对上述接收机的多标准维特比解码器设计是一个热点问题。本文针对LTE、WiMAX、CDMA2000、GSM和TD-SCDMA,提出了一种可重构的高性能维特比解码器设计方案。所提出的灵活架构支持多项式重构,约束长度为5 ~ 9,码率为1/2、1/3、1/4。同时支持咬尾和零格终止两种模式。为了降低解码延迟和复杂度,采用了前向回溯方法和滑动窗口管道技术。仿真结果表明,在时钟频率为600MHz时,其最大解码吞吐量为1.15Gbps。最后,其面积约为0.2mm2,功耗约为46 mw,这是根据synosis DC和TSMC 28nm标准电池库估算的。
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