A simplified methodology for complex analog module layout generation

Abstract

Analog layout design automation has been evolving constantly and several attempts have been made to find a solution for analog synthesis. Due to the complexity of analog design problem it is difficult to find a single approach which can be readily accepted by the industry. The optimization based full analog synthesis tools are quick but does not capture layout engineers' expertise and therefore produce sub optimal layout. The semi-automated layout tools help layout engineers considerably however the layout creation cycle time is still at unacceptable level for time-consuming analog designs. This paper presents a simplified methodology for generating complex analog modules layout using template driven parameterized cells to reduce layout creation cycle time significantly while meeting the layout designers need. The paper discusses step by step approach of developing a placement and routing template to capture layout engineers' expertise for complex analog modules and demonstrates its effectiveness by implementing a triple cascode amplifier super-pCell which is being used in pipeline Analog to Digital Converts. The implemented methodology is very flexible and fully controllable so that designers can easily create a layout with additional design requirements and constraints quickly. The proposed approach is successfully adopted by layout engineers and as a result, the required layout resources for a design are reduced significantly whereas layout engineers' efficiency is improved significantly.