A parallel router architecture for high speed LAN internetworking

Abstract

A parallel router architecture for processing network-layer protocols at FDDI (fiber distributed data interface) speeds is proposed. At high speeds the computing power of existing routers becomes the performance bottleneck (for processing small frame sizes). Hence, a completely different approach is required in designing a router. The opportunities of parallel processing in a network protocol are investigated. Several levels of parallel processing are considered, and an architecture for the most practical and feasible approach is proposed. The concept of a snoopy header cache is introduced. Algorithms for reducing the mean processing delay by balancing the load among the processors are discussed. The performance of the router is evaluated by analytic methods and is compared with simulation results. The results from both the analytic model and the simulator reinforce the choice of a header cache in a multiprocessor environment.<>