{"title":"Coevolvable hardware platform for automatic hardware design of neural networks","authors":"O. Hammami, K. Kuroda, Q. Zhao, K. Saito","doi":"10.1109/ICIT.2000.854208","DOIUrl":null,"url":null,"abstract":"This paper proposes a system for the automatic hardware design of neural networks based on cooperative coevolutionary paradigms and multiple reconfigurable devices. The authors' system is composed of a logic synthesis tool, multiple reconfigurable devices and an embedded processor executing the coevolutionary algorithm. The partitioning of the engineering design process follows current practices in hardware/software codesign based on both information on arrival rate /spl lambda/ of requests and the service time /spl mu/ of the reconfigurable devices. The system is suitable under some conditions for industrial applications such as a reactive system but also because it can be connected to multiple systems in a totally networked industrial environment which allows download of the same hardware configuration on multiple on ine devices.","PeriodicalId":405648,"journal":{"name":"Proceedings of IEEE International Conference on Industrial Technology 2000 (IEEE Cat. No.00TH8482)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE International Conference on Industrial Technology 2000 (IEEE Cat. No.00TH8482)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIT.2000.854208","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper proposes a system for the automatic hardware design of neural networks based on cooperative coevolutionary paradigms and multiple reconfigurable devices. The authors' system is composed of a logic synthesis tool, multiple reconfigurable devices and an embedded processor executing the coevolutionary algorithm. The partitioning of the engineering design process follows current practices in hardware/software codesign based on both information on arrival rate /spl lambda/ of requests and the service time /spl mu/ of the reconfigurable devices. The system is suitable under some conditions for industrial applications such as a reactive system but also because it can be connected to multiple systems in a totally networked industrial environment which allows download of the same hardware configuration on multiple on ine devices.