{"title":"A Reconfigurable Architecture for Stereo-Assisted Detection of Point-Features for Robot Mapping","authors":"J. Kalomiros, J. Lygouras","doi":"10.1109/RECONFIG.2009.41","DOIUrl":null,"url":null,"abstract":"A hardware-friendly procedure is presented for the extraction of point-features from stereo image pairs for the purpose of real-time robot motion estimation and 3-D environmental mapping. The procedure is implemented in reconfigurable hardware and is developed as a set of custom HDL library components ready for integration in a system-on-a-programmable-chip. The main hardware stages are a stereo accelerator, a left and right image corner detector and a stage performing left-right consistency check. For the stereo-processor stage we have implemented and tested a SAD-based component for local area-matching and a global-matching component based on a Maximum-Likelihood dynamic programming technique. The system includes a Nios II processor for data control and a USB 2.0 interface for host communication. Resource usage and 3D-mapping results are reported for different versions of the reconfigurable system.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Reconfigurable Computing and FPGAs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RECONFIG.2009.41","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A hardware-friendly procedure is presented for the extraction of point-features from stereo image pairs for the purpose of real-time robot motion estimation and 3-D environmental mapping. The procedure is implemented in reconfigurable hardware and is developed as a set of custom HDL library components ready for integration in a system-on-a-programmable-chip. The main hardware stages are a stereo accelerator, a left and right image corner detector and a stage performing left-right consistency check. For the stereo-processor stage we have implemented and tested a SAD-based component for local area-matching and a global-matching component based on a Maximum-Likelihood dynamic programming technique. The system includes a Nios II processor for data control and a USB 2.0 interface for host communication. Resource usage and 3D-mapping results are reported for different versions of the reconfigurable system.