A low power high speed error correction code macro using complementary pass transistor logic circuit

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI:10.1109/ASIC.1997.616970

L.K. Wang, H.H. Chen

引用次数: 2

Abstract

This paper describes the design and implementation of the complementary pass transistor logic (CPL) circuit in a CMOS macro design. The power, speed and noise margin of pass-transistor logic circuits are evaluated and the transistor sizes are optimized for noise margin and circuit performance. This circuit has been successfully implemented in a 64-bit Error Correction Code (ECC) and parity checking macro in the IBM S/390 CMOS processor and significantly improves the power and speed of the ECC macro performance.

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一种采用互补通型晶体管逻辑电路的低功耗高速纠错码宏

本文介绍了互补通型晶体管逻辑电路在CMOS宏设计中的设计与实现。对通管逻辑电路的功率、速度和噪声裕度进行了评估，并根据噪声裕度和电路性能对晶体管尺寸进行了优化。该电路已在IBM S/390 CMOS处理器的64位纠错码(Error Correction Code, ECC)和奇偶校验宏中成功实现，显著提高了ECC宏的功耗和速度性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

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