A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies

Abstract

Silicon photonics platforms are emerging as attractive solutions for low power and cost effective short/medium-reach optical interconnects. To overcome the intrinsic limitations of monolithically integrated photonics with electronics, STMicroelectronics has developed a 3D-compatible silicon photonics platform that implements in the FEOL only optical devices. Photonics Integrated Circuits are made compatible with 3D assembly of Electronic Integrated Circuits through the use of copper pillars. In this paper we present a 25Gbps Opto-Electronic receiver operating at 1310nm wavelength, consisting of an integrated waveguide Germanium photodiode interfaced by means of copper pillars to a 65nm CMOS amplification chain. The receiver demonstrates an Average Optical Power sensitivity at photodiode input, at a BER of 10-12, of -11.9dBm with a PRBS7 input signal, corresponding to a 97μApp TIA input current. The achieved sensitivity is ~6dB better than state-of-the-art monolithically integrated silicon photonics receivers, at comparable TIA and LA power consumption.