{"title":"A Bi-criterion Simulated Annealing Method to Solve Four-Stage Multiprocessor Open Shops with Dynamic Job Release Time","authors":"Yachih Tsai Huimei Wang, F. Chou","doi":"10.1109/CIIS.2017.61","DOIUrl":null,"url":null,"abstract":"The scheduling of chip sorting operation of LED manufacturing can be treated as a four-stage multiprocessor open shop problem, where each lot (job) with release time have four operations to be processed on a set of processing stages without predetermined necessary route. Each stage has one and more identical sorting machines. For the problem, we considered two objectives of minimizing makespan and total weighted tardiness simultaneously and proposed two simulated annealing (SA) methods to find out near pareto-optimal solutions. A series of computational experiments are conducted to evaluate the performance of the proposed SAs in comparison with exact solutions on various small-size problem instances. For large problems, the proposed SAs are also compared. The results show that performance of the SA1 algorithm was better than the SA2 whatever the test problems are small-size or large-size.","PeriodicalId":254342,"journal":{"name":"2017 International Conference on Computing Intelligence and Information System (CIIS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Computing Intelligence and Information System (CIIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CIIS.2017.61","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The scheduling of chip sorting operation of LED manufacturing can be treated as a four-stage multiprocessor open shop problem, where each lot (job) with release time have four operations to be processed on a set of processing stages without predetermined necessary route. Each stage has one and more identical sorting machines. For the problem, we considered two objectives of minimizing makespan and total weighted tardiness simultaneously and proposed two simulated annealing (SA) methods to find out near pareto-optimal solutions. A series of computational experiments are conducted to evaluate the performance of the proposed SAs in comparison with exact solutions on various small-size problem instances. For large problems, the proposed SAs are also compared. The results show that performance of the SA1 algorithm was better than the SA2 whatever the test problems are small-size or large-size.