A Voltage Level Shifter Design for High Performance Application in Near Threshold Voltage Regime

Abstract

An energy-efficient and optimized voltage CMOS voltage level shifter is proposed in this paper. There are several uses for the CMOS Voltage level shifters (LS) in power supply architecture. The voltage level shifter’s main function is to change the voltage level from low to high and vice versa. The proposed voltage LS circuit design uses a select signal (Vin) voltage switch logic, which accepts an input signal between 0.3 Volt and 0.6 Volt and produces an output signal with peak-to-peak voltage ranging from 1.2Volt to 0.6 Volt. The proposed LS circuit design is validated in ASAP7 7nm Fin-Fet technology, it outperforms a recently Wilson current mirror level shifter with Zero threshold voltage architecture in terms of latency and power dissipation by 42.76% and 39.6%, respectively. Power consumption and propagation delay are both significantly minimized by the proposed design topology.