A dual-rail LUT for reconfigurable logic using null convention logic

Abstract

Both asynchronous and reconfigurable techniques are likely to become increasingly important in the future due to greater device unreliability and variability at nano-scale dimensions. One promising asynchronous technique, Null Convention Logic (NCL) is a symbolically complete quasi-delay insensitive logic system that is inherently self-determined, locally autonomous and self-synchronizing. As current FPGA devices are set up for clocked synchronous logic they are not well suited to reconfigurable asynchronous systems. A reconfigurable block supporting NCL that is intended to form one component of a FPGA organization is proposed and analyzed. Both single-rail and dual-rail LUTs are described. The block design and layout is described and analyzed using an advanced 45nm bulk CMOS fabrication process.