{"title":"A 0.2 ‒ 1.2GHz Adaptive Bandwidth PLL with Controllable KVCO","authors":"Chang-Yu Song, Se-Hyeon Cho, Young-Chan Jang","doi":"10.1109/ISOCC53507.2021.9613999","DOIUrl":null,"url":null,"abstract":"An adaptive bandwidth phase-locked loop (PLL) that can control the gain (KVCO) of a voltage-controlled oscillator (VCO) is proposed to improve time jitter even with frequency changes in the reference clock of the PLL. The KVCO of the VCO is adaptively controlled according to the frequency of the reference clock by a KVCO controller consisting of a flash analog-to-digital converter. The proposed adaptive bandwidth PLL is designed by using a 55-nm CMOS process with a supply of 1.2 V. When the frequency of the output clock of the PLL is 200 MHz, ωUGB/ωREF is improved from 0.24 to 0.087 by controlling the KVCO. Also, its peak-to-peak time jitter is improved by 47 % from 10.6 ps to 5.54 ps.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 18th International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC53507.2021.9613999","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An adaptive bandwidth phase-locked loop (PLL) that can control the gain (KVCO) of a voltage-controlled oscillator (VCO) is proposed to improve time jitter even with frequency changes in the reference clock of the PLL. The KVCO of the VCO is adaptively controlled according to the frequency of the reference clock by a KVCO controller consisting of a flash analog-to-digital converter. The proposed adaptive bandwidth PLL is designed by using a 55-nm CMOS process with a supply of 1.2 V. When the frequency of the output clock of the PLL is 200 MHz, ωUGB/ωREF is improved from 0.24 to 0.087 by controlling the KVCO. Also, its peak-to-peak time jitter is improved by 47 % from 10.6 ps to 5.54 ps.