Design of fault-tolerant clocks with realistic failure assumptions

Abstract

The authors address the problem of designing fault-tolerant, phase-locked clocks in the presence of different types of clock failures and show that significant improvements in hardware complexity and reliability can be achieved when failed clock modules are partitioned into two classes: malicious and nonmalicious. They show that the condition N>2t+max(t1, 1) is necessary and sufficient to tolerate up to t failed clock modules out of which a maximum of t1 can behave maliciously. The practical value of this design concept is demonstrated by examples.<>