A design space exploration framework for reduced bit-width Instruction Set architecture (rISA) design

Abstract

Code size is a critical concern in many embedded system applications, especially those using RISC cores. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32 bit) Instruction Set, and a narrow, space-efficient (usually 16 bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This feature (termed rISA) can potentially reduce the code size by up to 50% with minimal performance degradation. However, contemporary processors incorporate only a simple rISA feature with severe restrictions on register accessibility. We present a compiler-in-the-loop Design Space Exploration framework that is capable of exploring various interesting rISA designs. We also present experimental results using this framework and show rISA designs that improve on the code size reduction obtained by existing rISA architectures.