VLSI Architecture of 1.264 Block Size Decision based on Rate-Distortion Optimization

Abstract

A novel approach to hardware implementation of H.264 block size decision is proposed, which is based on rate-distortion (RD) optimization. Utilization of RD cost for block size decision can improve up to 2.0 dB of PSNR in compared with conventional SAD/SATD based approaches. However, calculation of RD cost for a block incurs considerable computational costs since distortion can be determined only after completing the whole encoding processes of the block. Thus the proposed approach simplifies VLC process and our hardware employs 7 stage pipeline architecture for the cost calculation. As a result, the proposed architecture, which can be implemented by 20k gates, achieves real-time processing of SD (720times480) frames at a rate of 30 fps in 23.7 MHz operation