PEPPER-a timing driven early floorplanner

Abstract

With increasing chip complexities and the requirement to reduce design time, early analysis is becoming increasingly important in the design of performance critical CMOS chips. As clock rates increase rapidly, interconnect delay consumes an appreciable portion of the chip cycle time, and the floorplan of the chip significantly affects its performance. This paper describes a system for early floorplan analysis of large designs. The floorplanner is designed to be used in the early stages of system design, to optimize performance, area and wireability targets before detailed implementation decisions are made. Most floorplanners which claim to optimize timing work only on a subset of paths during the floorplanning process. One novel feature of our floorplanner is that it performs static timing analysis during the floorplan optimization process, instead of working on a subset of the paths. The floorplanner incorporates various interactive and automatic floorplanning capabilities. The paper describes the floorplanning capabilities and algorithms as well as our experiences in using the tool.