{"title":"A new expandable 2D systolic array for DFT computation based on symbiosis of 1D arrays","authors":"S. He, M. Torkelson","doi":"10.1109/ICAPP.1995.472165","DOIUrl":null,"url":null,"abstract":"A new expandable 2-dimensional systolic array consisting of N homogeneous processing elements in a rectangular structure to compute DFT is proposed. A DFT of size N=M/sup 2/ can be computed in 2M steps of pipelined operations, achieving the optimal area-time complexity of AT/sup 2/=O(N/sup 2/). The orthogonal pipelining of the processing is obtained by exploiting the symbiosis between 1-dimensional systolic arrays of H.T. Kung (1980) and L.W. Chang and M.Y. Chen (1988). Compared with another 2D array based on \"sandwiched\" triple matrix product, the presented approach integrates the twiddle factor multiplication into the row transform. This not only reduces computational complexity and the size of coefficient matrix, but also eliminates the twiddle factor preloading procedure. DFT of size 2/sup L/N can be readily computed with 2/sup L/ N-size arrays abutted together. VHDL modules have been written and successfully simulated for the proposed architecture.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAPP.1995.472165","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A new expandable 2-dimensional systolic array consisting of N homogeneous processing elements in a rectangular structure to compute DFT is proposed. A DFT of size N=M/sup 2/ can be computed in 2M steps of pipelined operations, achieving the optimal area-time complexity of AT/sup 2/=O(N/sup 2/). The orthogonal pipelining of the processing is obtained by exploiting the symbiosis between 1-dimensional systolic arrays of H.T. Kung (1980) and L.W. Chang and M.Y. Chen (1988). Compared with another 2D array based on "sandwiched" triple matrix product, the presented approach integrates the twiddle factor multiplication into the row transform. This not only reduces computational complexity and the size of coefficient matrix, but also eliminates the twiddle factor preloading procedure. DFT of size 2/sup L/N can be readily computed with 2/sup L/ N-size arrays abutted together. VHDL modules have been written and successfully simulated for the proposed architecture.<>