Gate Length Engineering Impact of Sub-10 nm GaN-Based DG-MOSFETs

Abstract

Gallium nitride based DG-MOSFETs with multiple gate lengths has been designed for the next generation logic applications. SILVACO ATLAS has been used to access Nonequilibrium Green’s function. The device turn on and turn off voltage (Gate-Source) is respectively, $\text{V}_{\mathbf {GS}} =$ 1 V (ON-state) and $\textbf{V}_{\mathbf {GS}} =$ 0 V (OFF-state). To improve high-speed performance from the concept of solid state device physics, effects of changing various characteristics for a different gate length of DG-MOSFETs were studied. Effects of the device are analyzed by varying various gate length ($\textbf{L}_{\mathbf {G}} =$6 nm to 10 nm). The device performance metrics such as $\textbf{I}_{\mathbf {ON}}$, sub threshold slope (SS) and drain induced barrier lowering (DIBL) has been done for multiple gate lengths. The simulated device verifies GaN-based DG-MOSFETs for various gate length for the next generation high speed, high performance (HP) and logic applications and VLSI technology.