De-Cache: A novel caching scheme for large-scale NoC based multiprocessor systems-on-chips

Abstract

Multi-level caches are used in multiprocessor systems to exploit locality of data and decrease the bandwidth demands on the network. Apart from exploiting locality in large-scale networks, we must also amortize the cost of distant communication so as to reduce memory request latency which is a critical determinant of multiprocessor performance. Our proposed architecture called the De-Cache ($De) architecture exploits the nature of the network-on-chip (NoC) structure by introducing what we called detour caches to store data from the most distant physical memory locations closer to the requesting node. Our experiments show that by using our proposed $De architecture we can decrease the memory request latency up to approximately 29.0% with very little degradation to the network performance.