Design Space Exploration for Rapid Development of DSP Applications

Abstract

In this paper a new methodology for accelerating the development cycle of DSP applications is presented. This methodology is composed of three steps 1) algorithm design with Matlab (mathworks), 2) algorithmic-level characterization and parallelism exploration using Design-Trotter SoC framework (LESTER/CISS) and 3) FPGA hardware synthesis with DK Design Suite (Celoxica). We have applied the proposed methodology to explore the design space of a RAKE receiver. The results show that by using this methodology, designers can rapidly converge from specification phases to the final synthesis of the system. The parallelism information provided by Design-Trotter has been shown extremely useful to develop the Handel-C description of the application, enabling a rapid synthesis of the system with DK Design Suite. The time-to-market factor is thus significantly reduced