{"title":"VLSI design of Extreme Value Detection based fast algorithm for H.264/AVC intra prediction","authors":"Chen-Hsien Miao, Chih-Peng Fan","doi":"10.1109/ICICS.2013.6782829","DOIUrl":null,"url":null,"abstract":"In this paper, an efficient fast algorithm called Boundary-aided Extreme Value Detection (BEVD) is applied to predict the best direction mode, excluding the DC mode, for H.264/AVC fast intra-mode decision. The BEVD-based two-step edge detection can predict luma-4×4, luma-16×16, and chroma-8×8 modes effectively. Simulation results show that the proposed BEVD method reduces encoding time by 63 %, and requires a bit-rate increase of approximately 1.7 %, and a decrease in peak signal-to-noise ratio (PSNR) by approximately 0.06 dB in CIF sequences, compared with the H.264/AVC JM 14.2 software. The proposed BEVD processor includes the memory unit, the system controller, and the BEVD core module. With TSMC 0.18 μm CMOS process, the proposed BEVD processor requires 16.4 K gates and performs the maximum operational frequency up to 71 MHz, and can be applied to the real-time HD format video encoding.","PeriodicalId":184544,"journal":{"name":"2013 9th International Conference on Information, Communications & Signal Processing","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 9th International Conference on Information, Communications & Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICS.2013.6782829","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, an efficient fast algorithm called Boundary-aided Extreme Value Detection (BEVD) is applied to predict the best direction mode, excluding the DC mode, for H.264/AVC fast intra-mode decision. The BEVD-based two-step edge detection can predict luma-4×4, luma-16×16, and chroma-8×8 modes effectively. Simulation results show that the proposed BEVD method reduces encoding time by 63 %, and requires a bit-rate increase of approximately 1.7 %, and a decrease in peak signal-to-noise ratio (PSNR) by approximately 0.06 dB in CIF sequences, compared with the H.264/AVC JM 14.2 software. The proposed BEVD processor includes the memory unit, the system controller, and the BEVD core module. With TSMC 0.18 μm CMOS process, the proposed BEVD processor requires 16.4 K gates and performs the maximum operational frequency up to 71 MHz, and can be applied to the real-time HD format video encoding.