K. Das, Kogara Naveen Kumar, P. Mouli, M. Srivastava
{"title":"A New Generalized Grounded Impedance Scaling Configuration with Electronic/Resistor Tunability","authors":"K. Das, Kogara Naveen Kumar, P. Mouli, M. Srivastava","doi":"10.1109/SPIN.2019.8711599","DOIUrl":null,"url":null,"abstract":"In this research article, an active configuration is proposed which acts similar to a impedance multipliar configuration. This configuration is able to increase or decrease the impedance of any grounded passive network. The presented circuit configuration employs two VDCCs and three grounded resistances along with the impedance to be multiplied. The scaling of impedance can be achieved through resistance variation or bias current variation. The use of only grounded passive elements enhance the suitability for on-chip integration. The working of the presented design has been investigated under non-ideal environment. The validation of behavior of the proposed multiplier circuit has been confirmed by designing and simulating an active filter. All the simulations have been performed in PSPICE Environment with $0.18\\ \\mu\\mathrm{m}$ CMOS technology.","PeriodicalId":344030,"journal":{"name":"2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPIN.2019.8711599","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this research article, an active configuration is proposed which acts similar to a impedance multipliar configuration. This configuration is able to increase or decrease the impedance of any grounded passive network. The presented circuit configuration employs two VDCCs and three grounded resistances along with the impedance to be multiplied. The scaling of impedance can be achieved through resistance variation or bias current variation. The use of only grounded passive elements enhance the suitability for on-chip integration. The working of the presented design has been investigated under non-ideal environment. The validation of behavior of the proposed multiplier circuit has been confirmed by designing and simulating an active filter. All the simulations have been performed in PSPICE Environment with $0.18\ \mu\mathrm{m}$ CMOS technology.