A 64-dB spurious free dynamic range CMOS baseband analog chain for IEEE 802.11a/b/g WLAN

Abstract

For the IEEE 802.11a/b/g wireless local area network (WLAN) applications, a receiver baseband analog (BBA) chain is designed. To improve performances of linearity and noise, an optimum allocation of gain and filter order of each block is performed. The fully integrated BBA chain is fabricated in 0.13µm 1-ploy 6-metal CMOS technology. The 3-dB bandwidth is tunable from 7.1MHz to 12.2MHz with digitally controlled switched capacitor array. An input-referred noise voltage (IRN) of 32.2 nV/√Hz at a gain of 60.8 dB and an input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0 dB are obtained. The total current consumption of the receiver BBA chain of 10 mA is obtained and the chip occupies 1.32mm2. Finally, the excellent SFDR performance of 63.9 dB is achieved.