Coverage of Meta-Stability Using Formal Verification in Asynchronous Gray Code FIFO

Abstract

In Formal Verification Environment, setup time and hold time are not honored by formal verification tool. To analyze the impact of metastability on functionality of the design in formal verification environment, buffer has been designed. Buffer induces the delay of either ‘0’, ‘1’ or ‘2’ clock cycles leading to metastability in the pointers of Asynchronous Gray Code FIFO in formal verification environment. Reference code has been written which describe the functionality of Asynchronous Gray Code FIFO in ideal case. Using formal equivalence checking, output of FIFO obtained from design provided by the designer, is compared with the output obtained from the reference code of FIFO. Formal verification properties are written to do the verification of the design and check if the design is working as predicted specifications. Coverage written ensures no corner case is skipped which may lead to escapism of potential design bugs. The command language script containing the verification program has been run to invoke the JasperGold Tool. Comparative analysis has been done between the waveforms obtained from the design including a buffer and the design without including a buffer. If both the waveforms are not same which means metastability has influenced the functionality of the design. So, to overcome the effect of metastability on functionality of the design, there is need to add more synchronizers in the design. While if the waveforms obtained from the design with and without buffer are same, it means synchronizers / Meta flops already present in the design are enough to deal with the metastability which may arise during functioning of the design.