VLSI design for SC-based speaker recognition

Abstract

This work presents an efficient VLSI architecture design for sparse coding (SC)-based speaker recognition system. The proposed system first extracts the linear predictive cepstral coefficients (LPCCs). Then, we applied orthogonal matching pursuit (OMP) for sparse coding and using the sparse coefficients as feature to do classification task. To speed up the computation time, our proposed chip comprises a LPCC module and an OMP module. The LPCC module computes the linear predictive coefficients (LPCs) and then converts LPCs to LPCCs. The OMP module includes residual unit, atom selection unit, QR decomposition unit, triangular matrix inverse unit and matrix multiplication unit. This designed chip has ability to handle a large dictionary size for sparse coding in OMP modules. The prototype chip is implemented using TSMC 90 nm CMOS technology on a die with a size of approximately 1.9×1.9 mm2.