Optimization of phase noise in a PLL circuit design

Abstract

The paper describes the effect of using different reference oscillator frequencies in a PLL circuit. Driving the PLL circuit with reference oscillator at different frequencies results in varied phase noise performance. The objective is to find out the reference frequencies along with other related parameters at different conditions thus yielding minimized spurs and optimal phase noise of the PLL system. The results can provide a guideline on the oscillator frequency selection resulting in improvising the phase noise characteristics of the PLL system along with its trade-off with the minimization of reference spurs.