M. Ghasemzadeh, A. Soltani, Amin Akbari, K. Hadidi
{"title":"Fast and accurate fractional frequency synthesizer in 0.18μm technology","authors":"M. Ghasemzadeh, A. Soltani, Amin Akbari, K. Hadidi","doi":"10.1109/MIXDES.2015.7208537","DOIUrl":null,"url":null,"abstract":"A 900MHz frequency synthesizer is presented in this article. The purpose of the proposed architecture is to minimize lock time in Phase-Locked Loops (PLLs). The structure has been simulated by HSPICE software in a typical 0.18um CMOS technology at the supply voltage of 1.8V. Simulation results prove that the designed frequency divider locks instantly that is a lower lock time compared to conventional PLLs.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"30 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2015.7208537","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A 900MHz frequency synthesizer is presented in this article. The purpose of the proposed architecture is to minimize lock time in Phase-Locked Loops (PLLs). The structure has been simulated by HSPICE software in a typical 0.18um CMOS technology at the supply voltage of 1.8V. Simulation results prove that the designed frequency divider locks instantly that is a lower lock time compared to conventional PLLs.
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