Vedic Divider: A Novel Design for Deconvolution Algorithm based on Vedic Math

Abstract

Convolution and deconvolution are commonly employed in digital signal processing. Binary division is used in the field of digital image processing for image restoration, red-eye removal, and blur reduction via deconvolution operations. Long sequences must commonly undergo convolution and deconvolution comparable to DSP in many applications. The essential prerequisite for speed in any application is an increase in the speed of its fundamental building block. Both convolution and deconvolution have a central component known as a multiplier or divider. It is the most important component of the system, yet it is also the slowest and most time-consuming. Many approaches for increasing the multiplier and divider's speed have been explored, but the Vedic multiplier and divider are currently the focus of interest. Because it operates more swiftly and with less energy. In this work, the convolution and deconvolution modules are accelerated using Vedic multiplier and divider. Xilinx ISE 14.7 can be used to accomplish this division algorithm's operation. The suggested design is contrasted with current FPGA topologies, including the non-restoring division Algorithm and other Vedic Dividers (Paravartya Sutra, Nikhilam Sutra).