Scan Delay Testing of Nanometer SoCs

Abstract

Delay defects that degrade performance and cause timing related reliability failures are emerging to be a major concern in nanometer technologies. Extensive at-speed functional testing to screen out such defects can be prohibitively expensive. Scan based structural delay tests are being pursued as a possible cost effective solution to this problem. However, recent research indicates that several formidable challenges must be overcome before such an approach can be fully effective. These include poor delay test coverage, and inaccuracies in the observed circuit timing due to false paths, power supply noise, clock stretching etc. This tutorial aims at a comprehensive discussion of these challenges and proposed solutions, aided by data from recently published industrial studies from Intel, IBM. TI, Freescale, LSI Logic, and universities.