Optimum Sizing of the Sleep Transistor in MTCMOS Technology

Abstract

Multi-threshold-voltage complementary metal-oxide semiconductor (MTCMOS) technology finds a wide variety of applications in reducing the subthreshold-leakage current in both combinational and sequential circuits. This is due to the fact that slightly increasing the threshold voltage causes a dramatic decrease in the subthreshold-leakage current. However, the decision on the sizing of the sleep transistor is a critical issue because there are various trade-offs that the designer must face with this respect. In this paper, the area, the static and dynamic-power consumption, and the time delay are investigated with respect to the aspect ratio of the sleep transistor with compact-form expressions derived for them. Accordingly, the optimal size of the sleep transistor is determined quantitatively. The results are discussed for NAND and NOR gates. The results obtained are based on adopting the Berkeley predictive technology model (BPTM) of the 22 nm CMOS technology with a power-supply voltage, VDD, equal to 0.8 V.