{"title":"A high spatial resolution 64-channel in-vivo neural recording system","authors":"M. Masoumi, G. Bertotti, S. Keil, R. Thewes","doi":"10.1109/MIXDES.2015.7208521","DOIUrl":null,"url":null,"abstract":"A high spatiotemporal resolution, wireline operation-based, in-vivo neural recording system is presented. The proposed system allows selecting 64 channels from 512 recording sites. The neural signals from the 64 selected sites are amplified, filtered, and finally multiplexed in the time domain. The output signals of each multiplexer are buffered, converted to the current domain, and then transferred to off-chip units for further signal processing purposes. The proposed chip is simulated in a standard 180 nm CMOS process. Estimated input referred noise in the frequency band from 1 Hz to 10 kHz is 5.1 μVrms, and the total power consumption amounts to 3.3 mW at a supply voltage of 1.8 V.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2015.7208521","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A high spatiotemporal resolution, wireline operation-based, in-vivo neural recording system is presented. The proposed system allows selecting 64 channels from 512 recording sites. The neural signals from the 64 selected sites are amplified, filtered, and finally multiplexed in the time domain. The output signals of each multiplexer are buffered, converted to the current domain, and then transferred to off-chip units for further signal processing purposes. The proposed chip is simulated in a standard 180 nm CMOS process. Estimated input referred noise in the frequency band from 1 Hz to 10 kHz is 5.1 μVrms, and the total power consumption amounts to 3.3 mW at a supply voltage of 1.8 V.