A 10-bit 50-MS/s SAR ADC with Split-Capacitor Array Using Unity-Gain Amplifiers Applied in FOG Systems

Abstract

This paper presents a 10-bit 50-MHz SAR ADC with novel split-capacitor array design for FOG (fiber optic gyroscope) systems. Unlike the traditional SAR ADCs using bridge capacitors for the split capacitor array, this design uses the unity-gain buffer to replace the bridge capacitor. Thus, the linearity and the immunity to the process variation of the capacitor array could be improved. Besides, the settling time and the size of the capacitor array are both reduced. The proposed design is implemented with a typical 40 nm CMOS process. The DNL and INL are simulated to be 0.51 LSB and 0.56 LSB, respectively. The simulated SNDR is 51.23 dB with the 12.5 MHz input signal to show ENOB=8.22 bits at the 50 MS/s sampling rate.