Hardware Architecture of Graph Neural Network-enabled Motion Planner (Invited Paper)

Lingyi Huang, Xiao Zang, Yu Gong, Bo Yuan
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引用次数: 1

Abstract

Motion planning aims to find a collision-free trajectory from the start to goal configurations of a robot. As a key cognition task for all the autonomous machines, motion planning is fundamentally required in various real-world robotic applications, such as 2-D/3-D autonomous navigation of unmanned mobile and aerial vehicles and high degree-of-freedom (DoF) autonomous manipulation of industry/medical robot arms and graspers.Motion planning can be performed using either non-learning- based classical algorithms or learning-based neural approaches. Most recently, the powerful capabilities of deep neural networks (DNNs) make neural planners become very attractive because of their superior planning performance over the classical methods. In particular, graph neural network (GNN)-enabled motion planner has demonstrated the state-of-the-art performance across a set of challenging high-dimensional planning tasks, motivating the efficient hardware acceleration to fully unleash its potential and promote its widespread deployment in practical applications.To that end, in this paper we perform preliminary study of the efficient accelerator design of the GNN-based neural planner, especially for the neural explorer as the key component of the entire planning pipeline. By performing in-depth analysis on the different design choices, we identify that the hybrid architecture, instead of the uniform sparse matrix multiplication (SpMM)-based solution that is popularly adopted in the existing GNN hardware, is more suitable for our target neural explorer. With a set of optimization on microarchitecture and dataflow, several design challenges incurred by using hybrid architecture, such as extensive memory access and imbalanced workload, can be efficiently mitigated. Evaluation results show that our proposed customized hardware architecture achieves order-of-magnitude performance improvement over the CPU/GPU-based implementation with respect to area and energy efficiency in various working environments.
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基于图神经网络的运动规划器硬件架构(特邀论文)
运动规划的目的是寻找机器人从起点到目标构型的无碰撞轨迹。作为所有自主机器的关键认知任务,运动规划在各种现实世界的机器人应用中都是必不可少的,例如无人驾驶移动和飞行器的2d / 3d自主导航以及工业/医疗机器人手臂和抓取器的高自由度自主操作。运动规划可以使用非基于学习的经典算法或基于学习的神经方法来执行。近年来,深度神经网络(dnn)的强大功能使神经规划器因其优于经典方法的规划性能而变得非常有吸引力。特别是,基于图形神经网络(GNN)的运动规划器在一系列具有挑战性的高维规划任务中展示了最先进的性能,激发了高效的硬件加速,以充分释放其潜力,并促进其在实际应用中的广泛部署。为此,本文对基于gnn的神经规划器的高效加速器设计进行了初步研究,特别是对作为整个规划管道关键组成部分的神经探索者进行了研究。通过对不同设计选择的深入分析,我们发现混合架构,而不是现有GNN硬件中普遍采用的基于均匀稀疏矩阵乘法(SpMM)的解决方案,更适合我们的目标神经探测器。通过对微体系结构和数据流进行优化,可以有效地缓解混合体系结构带来的大量内存访问和工作负载不平衡等设计难题。评估结果表明,我们提出的定制硬件架构在各种工作环境下的面积和能源效率方面比基于CPU/ gpu的实现实现了数量级的性能改进。
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