FGC: A Tool-flow for Generating and Configuring Custom FPGAs(Abstract Only)

Abstract

We introduce the FGC Toolflow, the only tool providing flexible custom-FPGA generation and configuration to-date. Currently, researchers building custom FPGAs must create for FPGA schematics and bitstreams by hand. Both tasks are prohibitively time intensive and error prone. Additionally, the simulation time for bitcell configuration is very long (often times longer than the functionality), making the verification of FPGA fabrics even more time consuming. Some existing toolflows and software packages designed to help with this process, but they only generate bitcell configurations, leaving schematics to be developed by hand. Others have limitations in circuit-level and architectural parameters, which prevent them from adequately exploring the FPGA design space. The FGC flow is the only flow available that generates a custom full-FPGA schematic from a single parameter text file, and generates the proper configuration bitstream for a target Verilog functionality. The parameter text file can accommodate 100s of different parameters, which include both circuit-level and architectural parameters to fully encompass the FPGA design space. The FGC flow generates both a schematic and a configuration bitstream for an FPGA with 100 CLBs (900,000 transistors) in only 8 minutes. The flow also generates simulation files, allowing the user to quickly set up and perform simulations to verify the FPGA and its configuration at the chip level with SPICE-level accuracy. This flow was used to create, verify, and test a taped-out ultra-low power FPGA.