A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip

H. Pham, S. Pillement, D. Demigny
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引用次数: 16

Abstract

Parallel computing is an important trend of embedded system. One possible response to increasing requirements in computational power is to distribute tasks over various processors and let these processors operate in parallel. Soft-core processors and FPGAs require low Non-Recurring Engineering costs to develop such multi-processors systems. Furthermore, certain FPGAs allow dynamic partial run-time reconfiguration, but their high sensitivity to electronic defects can cause the system disfunction. This paper presents a fault-tolerant multi-processor system-on-chip based on the dynamic reconfiguration of the entire platform. Also, a modification of the standard methodology of the runtime self-reconfiguration, who facilitates the complex modular concept design, is presented in this paper.
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动态可重构多处理器片上系统的容错层
并行计算是嵌入式系统发展的一个重要趋势。对于不断增长的计算能力需求,一种可能的应对方法是将任务分配到不同的处理器上,并让这些处理器并行运行。软核处理器和fpga需要较低的非重复性工程成本来开发这种多处理器系统。此外,某些fpga允许动态部分运行时重新配置,但它们对电子缺陷的高灵敏度可能导致系统故障。提出了一种基于整个平台动态重构的容错多处理器片上系统。此外,本文还对运行时自重构的标准方法进行了改进,为复杂的模块化概念设计提供了方便。
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