Artificial intelligence based scan vector reordering for capture power minimization

Abstract

Test Power is the major issues for the external testing of IP core based SoC. From a large pool of diverse available techniques for switching activity reduction during the external testing, only those schemes like ‘don't care bit filling’ and ‘reordering’ which do not require any modification in internal structure and do not demand use of any test development tool is used for SoC containing IP cores with hidden structure. The sequence of test vectors plays a significant role in capture power. The change in state of flipflop during capture depends upon the states of that flipflop in current scan-out vector and next scan-in vector. In this paper, the Artificial Intelligence Based Scan Vector Reordering (ASVR) is proposed to optimize the capture power reduction. This method uses very popular A∗ algorithm to reorder the test vectors to minimize the switching activity during capture operation.