Hardware acceleration of signature matching through multi-layer transition bit masking

Abstract

Content aware networking will be an integral feature in the next generation Residential Gateway Routers (RGR). Signature matching is the most time critical operation in content aware networking. Improving broadband speed necessitates the need for hardware acceleration of signature matching to manage and safeguard all the Internet of Things (IOT) clients connected to the smart home. Deterministic Finite Automata (DFA) allows the signature matching operation to be performed in linear time but has an exponential storage complexity. Bitmap based transition compression techniques are hardware friendly and can be used to achieve signature matching at multi gigabit throughput. However, its drawback is inefficient transition compression which results in storage of redundant transitions after the compression. We propose two bit masking techniques to efficiently compress transitions over existing bitmap based techniques. Compression ratios of 98% can be achieved using the proposed techniques, which in turn results in a 50% reduction of memory usage to store the compressed automata. A hardware acceleration architecture is proposed for each technique to decompress the transitions to achieve signature matching at multi gigabit rates.