The Ramification of Single Event Transient effect on Efficient Charge Recovery Logic circuit

Abstract

The evolution of modern Complementary Metal Oxide Semiconductor technology has led to the scaling of the transistor size to nanometers. This has resulted in significant advantages for integrated circuits such as higher speed, smaller circuit dimension, and lower operating voltage. However, this smaller dimension and lower operating voltage are highly susceptible to operational disturbances such as signal coupling, substrate noise, and single event effects caused by ionizing particles. Single event transient occurs whilst a excessive power particle hits a time independent logic circuit. The charge unloaded by these particles root a temporary voltage disturbance to load incorrect data. In this work, the impact of Single Event Transient on different parameters associated with Efficient Charge Recovery Logic circuit was analyzed. The technology node used for this analysis is 180 nanometers and 90 nanometers using Cadence Virtuoso.The result shows that on scaling the effect of Single Event Transient increases and the power dissipation is also increased by 32.4% .