The design and implementation of the TRIPS prototype chip

Abstract

This article consists of a collection of slides from the authors' conference presentation. They conclude that: distributed microarchitecture acknowledges and tolerates wire delay and scalable protocols tailored for distributed components. Tiled microarchitecture simplifies scalability and improves design productivity. The next step for instruction-level parallelism is EDGE ISA enables increased ILP while also exploiting coarser types of parallelism.