Ziyi Li, Leifeng Ruan, Chengqiang Yao, Yao Dong, Na Cui
{"title":"A Best Practice of 5G Layer 2 Network on Intel Architecture","authors":"Ziyi Li, Leifeng Ruan, Chengqiang Yao, Yao Dong, Na Cui","doi":"10.1109/GCWkshps45667.2019.9024643","DOIUrl":null,"url":null,"abstract":"This paper investigates a 5G layer 2 network software architecture design on Intel architecture with best practice. We consider to utilize both CPU and hardware acceleration units to implement layer 2 protocols according to 3rd Generation Partnership Project (3GPP). By considering different split options in centralized unit and distributed unit, the proposed software architecture is proved to be able to suit for both scenarios, as well as small cell and macro cell deployment scenarios. Numerical results show that the proposed architecture can be realized on Intel® Xeon® processors with pretty good performance, with high throughput, minimum latency and minimum CPU costs.","PeriodicalId":210825,"journal":{"name":"2019 IEEE Globecom Workshops (GC Wkshps)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Globecom Workshops (GC Wkshps)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GCWkshps45667.2019.9024643","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper investigates a 5G layer 2 network software architecture design on Intel architecture with best practice. We consider to utilize both CPU and hardware acceleration units to implement layer 2 protocols according to 3rd Generation Partnership Project (3GPP). By considering different split options in centralized unit and distributed unit, the proposed software architecture is proved to be able to suit for both scenarios, as well as small cell and macro cell deployment scenarios. Numerical results show that the proposed architecture can be realized on Intel® Xeon® processors with pretty good performance, with high throughput, minimum latency and minimum CPU costs.
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