{"title":"Reduced QRD-M detector in MIMO-OFDM systems with partial and embedded sorting","authors":"Yuanbin Guo, D. McCain","doi":"10.1109/GLOCOM.2005.1577378","DOIUrl":null,"url":null,"abstract":"In this paper, we present a reduced QRD-M matrix symbol detector in MIMO-OFDM systems. The QRD-M algorithm first decomposes the MIMO channel matrix into upper triangular matrix and applies a limited tree search to approximate the maximum-likelihood detector. The metric update is reduced from O(4.5 MC) to O(1.5 MC) by extracting the commonality. We then propose a partial quick-sort procedure and an embedded insert sort to achieve almost linear sorting. In the second part, we present efficient VLSI architectures utilizing the parallelism between subcarriers and design the pipelining in the multi-stage MIMO processing. The real-time architecture is implemented in an FPGA-based hardware accelerator with compact form factor, which achieves up to 100/spl times/ speedup in the simulation time.","PeriodicalId":319736,"journal":{"name":"GLOBECOM '05. IEEE Global Telecommunications Conference, 2005.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"GLOBECOM '05. IEEE Global Telecommunications Conference, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLOCOM.2005.1577378","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
In this paper, we present a reduced QRD-M matrix symbol detector in MIMO-OFDM systems. The QRD-M algorithm first decomposes the MIMO channel matrix into upper triangular matrix and applies a limited tree search to approximate the maximum-likelihood detector. The metric update is reduced from O(4.5 MC) to O(1.5 MC) by extracting the commonality. We then propose a partial quick-sort procedure and an embedded insert sort to achieve almost linear sorting. In the second part, we present efficient VLSI architectures utilizing the parallelism between subcarriers and design the pipelining in the multi-stage MIMO processing. The real-time architecture is implemented in an FPGA-based hardware accelerator with compact form factor, which achieves up to 100/spl times/ speedup in the simulation time.