Performance Analysis of Synchronizer and Measurement of Metastability

Abstract

There are so many applications which require more than one clock for their application. The transmitter works on one clock frequency and the receiver may work on another frequency. Due to this difference in frequencies between the transmitter and receiver causes the slower data transfer operation depending upon the transmitter frequency and sometimes there may be data loss. So in order to synchronize the data between them there is a need of synchronizer. The synchronizer plays an important role for proper communication between the transmitter and receiver. Another aspect of communication is reliability of data transfer and this can be determined and directly controlled by synchronizer. Hence the analysis of synchronizer plays vital role in an effective communication. The input to the synchronizer is asynchronous in nature so sometimes the synchronizer fails to synchronize the communication and this is called as metastability. Metastability states are common in digital circuits, and synchronizers are must to protect their fatal effects. Originally, they were required when reading an asynchronous input (namely, not synchronized with the clock so it might change exactly when sampled). Now, with multiple clock domains on the same chip, synchronizers are required when on-chip data crosses the clock domain boundaries.. This can be achieved by the parameters of synchronizer. The proposed architecture shows the analysis of the reliable data transfer and metastability.