Parasitic-aware gm/ID-based many-objective analog/RF circuit sizing

Abstract

Accurate parasitic consideration in analog/RF circuit synthesis becomes more essential since layout-dependent effects become more influential in the advanced technologies. In this paper, a gm/ID-based circuit sizing method, which takes into account both device intrinsic parasitics and interconnect parasitics, is proposed as the first stage of a hybrid sizing optimization. In the second stage, a many-objective evolutionary algorithm is applied to refine the sizing solutions. The proposed methodology has been utilized to optimize multiple performances of an analog dynamic differential comparator and a RF circuit in the advanced CMOS technology. The experimental results have exhibited high efficacy of our proposed parasitic-aware hybrid sizing methodology.