{"title":"A GNSS receiver using band-pass continuous-time delta-sigma modulator","authors":"Anis Ben Arfi, F. Ghannouchi, R. Barrak, C. Rebai","doi":"10.1109/MMS.2014.7088939","DOIUrl":null,"url":null,"abstract":"This paper addresses some of the considerations related to the design and implementation of multiband Global Navigation Satellite System (GNSS) receivers. In this work, the impact of the application of band-pass continuous-time delta-sigma modulation on GNSS signals was also examined. In order to facilitate the implementation of the multiband delta-sigma based GNSS receiver, a modulator architecture that is based on an all-digital feedback loop using zero-insertion upsampling was adopted and frequency downscaling technique was used. The latter consists on reducing the operating frequency of the system, which makes the implementation on a field programmable gate array (FPGA) possible.","PeriodicalId":166697,"journal":{"name":"Proceedings of 2014 Mediterranean Microwave Symposium (MMS2014)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 2014 Mediterranean Microwave Symposium (MMS2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MMS.2014.7088939","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper addresses some of the considerations related to the design and implementation of multiband Global Navigation Satellite System (GNSS) receivers. In this work, the impact of the application of band-pass continuous-time delta-sigma modulation on GNSS signals was also examined. In order to facilitate the implementation of the multiband delta-sigma based GNSS receiver, a modulator architecture that is based on an all-digital feedback loop using zero-insertion upsampling was adopted and frequency downscaling technique was used. The latter consists on reducing the operating frequency of the system, which makes the implementation on a field programmable gate array (FPGA) possible.