Low Power, High Performance PMOS Biased Sense Amplifier

Abstract

Sense amplifiers plays a significant role in terms of its recital, functionality and reliability of the memory circuits. In this paper two new circuits have been proposed. The proposed circuit is PMOS biased sense amplifier, which provides very high output impedance and has reduced sense delay and power dissipation. As such, the proposed circuit performs the identical operations as that of conventional circuits but with the reduced the sense delay and power consumption. The suggested sense amplifiers overall performance have been simulated and examined using Cadence virtuoso with gpdk 180 nm library parameters.