Optimal complex operator mapping

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI:10.1109/ASIC.1997.617008

H. Savoj, Duen-Jeng Wang, D. Hoang, Chi-Lai Hiang

引用次数: 1

Abstract

This paper presents a RTL synthesis flow that considers area minimization in mapping to complex cells from a technology library. A mapping decision is made by examining the complete design, If a complex cell in the middle of a design has many redundancies because of the boundary conditions (inputs or outputs of the complex cell are somwehow related) the Boolean equations for the complex cell are simplified and the cell is implemented from single-output Boolean gates. Otherwise, the complex cell from the library is retained. This approach not only achieves smaller design but also improves the testability of the overall design.

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最优复算子映射

本文提出了一种RTL合成流程，该流程考虑了从技术库映射到复杂细胞的面积最小化。如果设计中间的复杂单元由于边界条件(复杂单元的输入或输出以某种方式相关)而具有许多冗余，则简化该复杂单元的布尔方程，并从单输出布尔门实现该单元。否则，将保留库中的复杂单元格。这种方法不仅实现了更小的设计，而且提高了整体设计的可测试性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

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