{"title":"Internal architecture of Alpha 21164 microprocessor","authors":"P. Bannon, J. Keller","doi":"10.1109/CMPCON.1995.512368","DOIUrl":null,"url":null,"abstract":"The internal architecture of a 1200 MIPS/600 MFLOPS (peak) high-performance CMOS ALPHA microprocessor chip is described. This second-generation implementation is the world's fastest microprocessor. It contains a quad-issue superscalar instruction unit, two 64-bit integer execution pipelines, and two 64-bit floating point execution pipelines. The memory unit and bus interface unit combine to form a high-perfomance memory sub-system with MP coherent writeback caches.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"41","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPCON.1995.512368","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 41
Abstract
The internal architecture of a 1200 MIPS/600 MFLOPS (peak) high-performance CMOS ALPHA microprocessor chip is described. This second-generation implementation is the world's fastest microprocessor. It contains a quad-issue superscalar instruction unit, two 64-bit integer execution pipelines, and two 64-bit floating point execution pipelines. The memory unit and bus interface unit combine to form a high-perfomance memory sub-system with MP coherent writeback caches.
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