A Run-Time Library for Parallel Processing on a Multi-core DSP

2013 3rd Eastern European Regional Conference on the Engineering of Computer Based Systems Pub Date : 2013-08-29 DOI:10.1109/ECBS-EERC.2013.14

N. Cetic, M. Popovic, Miodrag Djukic, Momcilo Krunic

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引用次数: 2

Abstract

Future of the computer based systems resides in the multi-core and many-core architectures. Thanks to availability of different multi-core processors, many parallelization tools and techniques emerged. However, majority of them rely on the shared memory architecture model, where data to multiple core processors is simply accessible. In this paper we present a simple hardware abstraction that targets features of a multi-core DSP processor with distributed memory architecture, aiming support for program parallelization. Both manual and automatic code parallelization approaches can use library routines described in this paper. By validating performance of multiple manually created test cases we demonstrate capabilities of presented approach. Performance is estimated by measuring time necessary for DMA data transfer between the cores using GPIO pins attached to the DSP. In addition, earlier developed C code parallelization technique for the same DSP is extended to use this library providing full working solution verified on real hardware.

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多核DSP并行处理运行库

基于计算机的系统的未来是多核和多核体系结构。由于各种多核处理器的可用性，出现了许多并行化工具和技术。然而，它们中的大多数依赖于共享内存体系结构模型，在这种模型中，传输到多个核心处理器的数据很容易访问。在本文中，我们提出了一个简单的硬件抽象，针对具有分布式内存架构的多核DSP处理器的特点，旨在支持程序并行化。手动和自动代码并行化方法都可以使用本文描述的库例程。通过验证多个手动创建的测试用例的性能，我们演示了所提出方法的能力。性能是通过测量使用GPIO引脚连接到DSP的核心之间的DMA数据传输所需的时间来估计的。此外，还扩展了早先开发的用于同一DSP的C代码并行化技术，以使用该库提供在实际硬件上验证的完整工作解决方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2013 3rd Eastern European Regional Conference on the Engineering of Computer Based Systems

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